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Full page photo print

Phase Locked Loops for Wireless Communications

Phase Locked Loops for Wireless Communications

Harmonic balance finite element method applications in nonlinear electromagnetics and power systems (Lu, Junwei Yamada, Sotoshi Zhao, Xiaojun) (z-lib.org)

Harmonic balance finite element method applications in nonlinear ...

PLL 设计仿真及应用

PLL 设计仿真及应用

斩波放大器输出纹波抑制方法综述张三锋

斩波放大器输出纹波抑制方法综述张三锋

锁相环相位噪声与环路带宽的关系分析

锁相环相位噪声与环路带宽的关系分析

电路分析

电路分析

Practical RF Circuit Design for Modern Wireless Systems_ Passive Circuits and Systems Volume I

Practical RF Circuit Design for Modern Wireless Systems_ Passive ...

使用电压基准进行设计的提示和技巧

使用电压基准进行设计的提示和技巧

Texas Instruments, Incorporated [ZHCC347,*]

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...

D.J. Foley;M.P. Flynn

ISSCC2021-1 3

ISSCC2021-1 3

VLSI Physical Design: From Graph Partitioning to Timing Closure

VLSI Physical Design: From Graph Partitioning to Timing Closure

Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu

精通开关电源设计（第2版）

精通开关电源设计（第2版）

Microsoft PowerPoint - PLLnoise_jitter0209.ppt [相容模式]

Microsoft PowerPoint - PLLnoise_jitter02[..] [相容模式]

低功耗逐次逼近寄存器模数转换器综述丁召明 (1)

低功耗逐次逼近寄存器模数转换器综述丁召明 (1)

数值分析

数值分析

运放仿真方法整理

运放仿真方法整理

Fundamentals of Layout Design for Electronic Circuits

Fundamentals of Layout Design for Electronic Circuits

Jens Lienig Juergen Scheible

Category: 2016 IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB);2016; ; ;10.1109/ICUWB.2016.7790413

A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process

A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process

Wenzha Yang & Yi Zhang & Enwen Dai & ZhiLin Feng & Wei Li