理工书库 lilin | Category: clock

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射频电路基础 (赵建勋,邓军) (Z-Library)

射频电路基础 (赵建勋,邓军) (Z-Library)

Computing the continuous discretely. Integer-point enumeration in polyhedra Beck, Matthias Robins, Sinai (z-lib.org)

Computing the continuous discretely. Integer-point enumeration ...

自动控制原理与设计（第6版） (富兰克林、鲍威尔。李中华译) (Z-Library)

自动控制原理与设计（第6版） (富兰克林、鲍威尔。李中华译) (Z-Library)

Verilog HDL Design Examples

Verilog HDL Design Examples

Joseph Cavanagh

CMOS Realization of OTA as an Application in Low Power Amplifier for Enhancing the Performance and Stability using 65 Nm Technology

CMOS Realization of OTA as an Application in Low Power Amplifier ...

Ghanshyam Singh, Md Hameed Pasha

COMS集成锁相环电路设计

COMS集成锁相环电路设计

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...

Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin

JSSC 202212

JSSC 202212

低压低功耗Sigma Delta调制器综述吕立山

低压低功耗Sigma Delta调制器综述吕立山

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Gabriel Rincon-Mora - Analog IC Design with Low-Dropout Regulators (LDOs) (Electronic Engineering) (2009)

Gabriel Rincon-Mora - Analog IC Design with Low-Dropout Regulators ...

Analog IC Design & Low-Dropout Regulators (LDOs) (Electronic Engineering) (2009) ...

ISSCC2021-SC4-Processor Clock Generation, Distribution, and Clock SensorManagement Loops

ISSCC2021-SC4-Pro[..] Clock Generation, Distribution, and Clock ...

Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6/e

Digital Design: With an Introduction to the Verilog HDL, VHDL, ...

M. Morris R. Mano & Michael D. Ciletti

MIMO-OFDM无线通信技术及MATLAB实现＝MIMO-OFDM WIRELESS COMMUNICATIONS WITH MATLAB

MIMO-OFDM无线通信技术及M[..] WIRELESS COMMUNICATIONS WITH MATLAB

（韩）YONG SOO CHO，JAEKWON KIM，WON YONG YANG，CHUNG G.KANG著；孙锴，黄威译

综合与Design Compiler

综合与Design Compiler

锁相环相位噪声与环路带宽的关系分析

锁相环相位噪声与环路带宽的关系分析

FPGA 全芯片 ESD 防护设计和优化

FPGA 全芯片 ESD 防护设计和优化

Signal Processing Algorithms for Communication and Radar Systems

Signal Processing Algorithms for Communication and Radar Systems

Category: clock

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm ...

Kuan-Yueh Shen & Syed Feruz Syed Farooq & Yongping Fan & Khoa Minh Nguyen & Qi Wang & Mark L. Neidengard & Nasser Kurd & Amr Elshazly