Distributed MOS varactor biasing for VCO gain equalization in ...
J. Mira & T. Divel & S. Ramet & J.-B. Begueret & Y. Deval
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai
Harmonic balance finite element method applications in nonlinear ...
未知
LOCK DETECTION CIRCUIT AND LOCK (56) Oct. 18, 2011 References ...
Session 17: DC-DC Converters
Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet
Xilinx, Inc.
A Basic Introduction to the gm ID-Based Design
适用于高速闪存的超快无片外电容LDO
Session 7: Imagers and Range Sensors
一种自参考结构的高速高精度片上时钟[..]
AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...
Cadence高速电路板设计
精通开关电源设计（第2版）
Session 4: Processors
基于嵌入式密勒补偿技术的LDO放大器设计
A bandgap reference using chopping for reduction of
Frequency Compensation of Op-amp and its types Circuit Digest
Embedded Mixed-Signal IP Development Methodology in 90nm CMOS ...
Rakesh H. Patel & William Bereza
Wideband RF PLL fractional/integer frequency synthesizer with ...
STMICROELECTRONICS