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JESD204 v7.2 LogiCORE IP Product Guide (PG066)
Xilinx, Inc.
数值分析
未知
Embedded Mixed-Signal IP Development Methodology in 90nm CMOS ...
Rakesh H. Patel & William Bereza
多频段匹配自动优化
Yue Xu
The Art of Analog Layout, Second Edition
Alan Hastings
RISC-V手册
Da
ISSCC2021-T7-Basic Design Approaches to Accelerating Deep Neural ...
Jespers-The gm ID Methodology, a sizing tool
asicon.2009.53514[..] Power Supply Rejection
16位高速CMOS流水线模数转换器[..] (1)
14990665645773625[..]
一种低静态电流瞬态增强的无电容型L[..]
Session 1: Plenary Session — Invited Papers
Session 32: Frequency Synthesizers
高精度带隙基准电压源的研究与设计
iData
Session 12
UVM实战（卷Ⅰ)
张强编著
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop ...
Yongsun Lee & Taeho Seong & Seyeon Yoo & Jaehyouk Choi