数值分析
未知
一种自适应补偿的宽输入LDO设计
【汉化】Static Timing Analysis for Nanometer DesignsA Practical ...
二级运放建立时间与相位裕度的分析与优化
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm ...
Kuan-Yueh Shen & Syed Feruz Syed Farooq & Yongping Fan & Khoa Minh Nguyen & Qi Wang & Mark L. Neidengard & Nasser Kurd & Amr Elshazly
Session 11: Advanced Wireline Links and Techniques
工作在亚阈值区CMOS OTA的研究
IEEE Std 802.11b-1999
IEEE Std 802.11ac™-2013, IEEE Standard for Information technology—Teleco[..] ...
LAN/MAN Standards Committee of the IEEE Computer Society
高速高精度ADC中基准电压源的研究与设计 (1)
PrimeTime User Guide
Synopsys, Inc.
高PSRR无电容型线性稳压器的研究与设计
LU HUNG
一种快速瞬态响应无片外电容LDO
MT-001: Taking the Mystery out of the Infamous Formula,'SNR ...
Walt Kester
ELKHOLY-DISSERTAT[..]
Katsuhiko Ogata
dynstab2/ThePirateBay
通信原理 第7版
樊昌信,曹丽娜编著
锁相环(PLL)电路设计与应用
(日)远坂俊昭 著 何希才译
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai