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电路分析

电路分析

DDR3存储器接口电路的设计与实现-ESD写得好

DDR3存储器接口电路的设计与实现[..]

综合与Design Compiler

综合与Design Compiler

CN101140511B-硅谷数模2010-Cascaded carry binary adder

CN101140511B-硅谷数模[..] carry binary adder

Microsoft Word - Chapter1 Importance of Impedance matching.doc

Microsoft Word - Chapter1 Importance of Impedance matching.doc

多频段匹配自动优化

多频段匹配自动优化

MOSAmpNoise.dvi

MOSAmpNoise.dvi

阻抗匹配与史密斯（Smith）圆图：基本原理

阻抗匹配与史密斯（Smith）圆图[..]

工程电路分析

工程电路分析

BSIM4 AND MOSFET MODELING FOR IC SIMULATION

BSIM4 AND MOSFET MODELING FOR IC SIMULATION

Hu, Chenming, Liu, Weidong

A 470-nA Quiescent Current and 92.7%/94.7% Efficiency DCT/PWM Control Buck Converter With Seamless Mode Selection for IoT Application

A 470-nA Quiescent Current and 92.7%/94.7[..] Efficiency ...

一种高摆幅软启动线性稳压源设计

一种高摆幅软启动线性稳压源设计

UVM实战（卷Ⅰ)

UVM实战（卷Ⅰ)

On-Chip Compensated Error Amplifier for

On-Chip Compensated Error Amplifier for

Aperture Uncertainty and ADC System Performance Application Note (AN-501)

Aperture Uncertainty and ADC System Performance Application ...

Analog Devices, Inc.

Traveling Wave Analysis of Partial Differential Equations Numerical and Analytical Methods with Matlab and Maple

Traveling Wave Analysis of Partial Differential Equations Numerical ...

Cadence PVS Developers Guide

Cadence PVS Developers Guide

Inc. Cadence Design Sys tems

控制之美卷1 (王天威) (Z-Library)

控制之美卷1 (王天威) (Z-Library)

Category: This IP core is used for building a PCI Express® Media Access Controller (MAC) layer. It supports 1/2/4/8/16-lane

PCI Express PHY v1.0 LogiCORE IP Product Guide

PCI Express PHY v1.0 LogiCORE IP Product Guide