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射频集成电路与系统

射频集成电路与系统

李智群王志功编著

相位噪声、通行链路预算

相位噪声、通行链路预算

低功耗的高速高精度运放设计

低功耗的高速高精度运放设计

A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process

A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process

Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Yin-Zu Lin

A comparative study of various current mirror configurations_ Topologies and characteristics

A comparative study of various current mirror configurations_ ...

Bhawna Aggarwal & Maneesha Gupta & A.K. Gupta

CMOS模拟集成电路设计与仿真实例：基于Hspice

CMOS模拟集成电路设计与仿真实例[..]

柯明道ESD简洁版

柯明道ESD简洁版

Design and Simulation of LNA using Advanced Design Systems (ADS)

Design and Simulation of LNA using Advanced Design Systems (ADS)

一种快速瞬态响应LDO的设计与实现

一种快速瞬态响应LDO的设计与实现

模拟电路设计——鲁棒性设计、Sigma-Delta转换器、射频识别技术 (模拟电路设计——鲁棒性设计、Sigma-Delta转换器、射频识别技术) (z-lib.org)

模拟电路设计——鲁棒性设计、Sig[..] (模拟电路设计——鲁棒性设计、Si[..] (z-lib.org)

Spice-Oriented Nonlinear Circuit Analysis Using Harmonic Balance Method

Spice-Oriented Nonlinear Circuit Analysis Using Harmonic Balance ...

高速数字电路设计中信号完整性分析与研究

高速数字电路设计中信号完整性分析与研究

Amplifiers, Comparators, Multipliers, Filters, and Oscillators; Second Edition

Amplifiers, Comparators, Multipliers, Filters, and Oscillators; ...

Tertulien Ndjountche

CMOS带隙基准源研究现状幸新鹏

CMOS带隙基准源研究现状幸新鹏

1.5Bit 级pipelined+ADC典型单级电路结构实现研究

1.5Bit 级pipelined+ADC典型单[..]

LOCK DETECTION CIRCUIT AND LOCK (56) Oct. 18, 2011 References Cited DETECTING METHOD

LOCK DETECTION CIRCUIT AND LOCK (56) Oct. 18, 2011 References ...

信号与系统习题详解奥本

信号与系统习题详解奥本

Session 21

Session 21

Category: This IP core is used for building a PCI Express® Media Access Controller (MAC) layer. It supports 1/2/4/8/16-lane

PCI Express PHY v1.0 LogiCORE IP Product Guide

PCI Express PHY v1.0 LogiCORE IP Product Guide