CMOS Circuit Design, Layout, and Simulation
Baker, R. Jacob
一个全差分运放电路的设计
Administrator
高速数字电路设计中信号完整性分析与研究
未知
VerilogA系统设计与仿真（可[..]
PHASE-INTERPOLATOR BASED PLL FREQUENCY SYNTHESIZER
基于ac620的fpga系统设计与[..]
5.0Gbps高速串行USB3.0[..]
CH01
Godming
MATLAB数字信号处理85个实用[..]
The Problem of PLL Power Consumption
Behzad Razavi
ISSCC2017-24 Visuals(2)
sido buck converter
Duyu Liu & Xinzhi Liu & Hao Chen & Shouming Zhong
Silicon-Germanium Heterojunction Bipolar Transistors (2002)
射频系统内低中频滤波器的设计和研究
简并点优化的高性能带隙基准电路 应建华
VLSI Physical Design: From Graph Partitioning to Timing Closure
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
基于延迟锁相环的时钟发生器设计
CMOS集成电路EDA技术
作者
IEEE Std 1801™-2018, IEEE Standard for Design and Verification ...
Design Automation Standards Committee of the IEEE Computer Society