半导体器件物理(原书第三版)中文版[..]
未知
一个全差分运放电路的设计
Administrator
Session 8: Ultra-High-Speed Wireline
lnaDesign2
FinFET Devices for VLSI Circuits and Systems
Samar K. Saha
二级运放建立时间与相位裕度的分析与优化
Digital Logic and Computer Design
M. MORRIS MANO
VerilogA系统设计与仿真（可[..]
CN105763219A-2016[..]
Memory systems_ cache, DRAM, disk -- Bruce Jacob, Spencer Ng, ...
A gm/ID Based Methodology for the Design of CMOS Analog Circuits ...
IEEE
LDO与VLDO的设计原理及性能测试
A 2-dB noise figure 900-MHz differential CMOS LNA - Solid-State ...
一种基于OTA的低功耗高速静态比较[..]
芯片漫游指南
Numerical Simulation of Optical Wave Propagation With Examples ...
Jason D. Schmidt
X-Parameters
DAVID E. ROOT
Delta-sigma ADC
jianggx
Verilog数字VLSI设计教程
【作 者】李林编著