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PrimeSim� XA User Guide

PrimeSim� XA User Guide

A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process

A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process

Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Yin-Zu Lin

[Behzad Razavi] Phase-Locking in High-Performance (BookFi)

[Behzad Razavi] Phase-Locking in High-Performance (BookFi)

[集成电路掩膜板设计].IC.Mask.Design

[集成电路掩膜板设计].IC.Ma[..]

模拟集成电路分析与设计

模拟集成电路分析与设计

Analysis and Design of CMOS Clocking Circuits for Low Phase Noise

Analysis and Design of CMOS Clocking Circuits for Low Phase ...

Woorham Bae & Deog-Kyoon Jeong

微带电路——清华

微带电路——清华

多采样率系统：采样率转换和数字滤波器组

多采样率系统：采样率转换和数字滤波器组

数字通信同步技术的MATLAB与FPGA实现 Altera Verilog版 [杜勇编著] 2015年版

数字通信同步技术的MATLAB与F[..] Altera Verilog版 [杜勇编著] 2015年版

模拟集成电路设计与仿真-何乐年

模拟集成电路设计与仿真-何乐年

PoleZero.dvi

PoleZero.dvi

一种基于LDO线性稳压器的放大器设计

一种基于LDO线性稳压器的放大器设计

Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance

Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller ...

Shih-An Yu & Peter R. Kinget

Ring PLL的详细设计博士论文

Ring PLL的详细设计博士论文

硅基压控振荡器的研究与设计电子科技大学彭羽

硅基压控振荡器的研究与设计电子科技大学彭羽

Session 16

Session 16

实用开关电源设计

实用开关电源设计

lnaDesign2

lnaDesign2

Category: Vivado

Vivado Design Suite User Guide: Logic Simulation (UG900)

Vivado Design Suite User Guide: Logic Simulation (UG900)

Xilinx PG153 LogiCORE IP AXI Quad Serial Peripheral Interface (SPI) v3.1, Product Guide

Xilinx PG153 LogiCORE IP AXI Quad Serial Peripheral Interface ...

JESD204 v7.2 LogiCORE IP Product Guide (PG066)

JESD204 v7.2 LogiCORE IP Product Guide (PG066)

AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)

AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP Product Guide (PG055)

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...

PCI Express PHY v1.0 LogiCORE IP Product Guide

PCI Express PHY v1.0 LogiCORE IP Product Guide