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Intro to Python forComputer Science and Data Science : Learning to Program with AI, Big Data and the Cloud

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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6/e

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开关功率变换器——开关电源的原理、仿真和设计（原书第3版） (张懋徐德鸿) (Z-Library)

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Category: This core implements a JESD204B interface supporting a line rate of up to 12.5 Gb/s on 1- 12 lanes using GTX or GTH transceivers in Zynq-7000 AP SoC devices

JESD204 v7.2 LogiCORE IP Product Guide (PG066)

JESD204 v7.2 LogiCORE IP Product Guide (PG066)