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学校代码 10530 学号 201110061316

学校代码 10530 学号 201110061316

基于延迟锁相环的时钟发生器设计

基于延迟锁相环的时钟发生器设计

Operation and Modeling of the MOS Transistor 3rd

Operation and Modeling of the MOS Transistor 3rd

CMOS Circuit Design, Layout, and Simulation

CMOS Circuit Design, Layout, and Simulation

Baker, R. Jacob

2014 PhD-Thesis BAG A Designer-Oriented Framework for the Development of AMS Circuit Generators

2014 PhD-Thesis BAG A Designer-Oriented Framework for the Development ...

模拟电子技术基础答案-第五版

模拟电子技术基础答案-第五版

现代控制系统第八版

现代控制系统第八版

射频接收机中模拟信道滤波器设计

射频接收机中模拟信道滤波器设计

A fast-settling CMOS op amp for SC circuits with 90-dB DC gain

A fast-settling CMOS op amp for SC circuits with 90-dB DC gain

K. Bult;G.J.G.M. Geelen

ISSCC2021-T12-compressed

ISSCC2021-T12-com[..]

数值分析

数值分析

Session 24: Advanced Embedded Memories

Session 24: Advanced Embedded Memories

Voltus-Fi Hierarchical IR Drop and EM Analysis

Voltus-Fi Hierarchical IR Drop and EM Analysis

Xilinx DS249 LogiCORE IP CORDIC v4.0, Data Sheet,

Xilinx DS249 LogiCORE IP CORDIC v4.0, Data Sheet,

高性能低压差线性稳压器研究与设计

高性能低压差线性稳压器研究与设计

天线（第三版）约翰克劳斯中文高清全本

天线（第三版）约翰克劳斯中文高清全本

开关电源控制环路设计

开关电源控制环路设计

Introduction to advance node feathers

Introduction to advance node feathers

Category: This core implements a JESD204B interface supporting a line rate of up to 12.5 Gb/s on 1- 12 lanes using GTX or GTH transceivers in Zynq-7000 AP SoC devices

JESD204 v7.2 LogiCORE IP Product Guide (PG066)

JESD204 v7.2 LogiCORE IP Product Guide (PG066)