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集成电路版图设计

集成电路版图设计

余华，师建英编著

HFIC chapter 7 low-noise amplifier design

HFIC chapter 7 low-noise amplifier design

控制之美卷1 (王天威) (Z-Library)

控制之美卷1 (王天威) (Z-Library)

CN106357266B-华为2016-锁定检测电路、方法及锁相电路-带offset电流

CN106357266B-华为20[..]

精通开关电源设计（第2版）

精通开关电源设计（第2版）

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...

Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin

AI算法工程师手册

AI算法工程师手册

GPS接收机内带镜像抑制的中频滤波器设计

GPS接收机内带镜像抑制的中频滤波器设计

Intel® Quartus® Prime Standard Edition User Guide Platform Designer

Intel® Quartus® Prime Standard Edition User Guide Platform Designer

Intel Corporation

Nios II Processor Reference Guide

Nios II Processor Reference Guide

Intel Corporation

ISSCC2021 Session 21

ISSCC2021 Session 21

CN104391533A-High-PSRR (power supply rejection ratio) LDO (low dropout regulator) circuit

CN104391533A-High[..] (power supply rejection ratio) LDO (low ...

A 2-dB noise figure 900-MHz differential CMOS LNA - Solid-State Circuits, IEEE Journal of

A 2-dB noise figure 900-MHz differential CMOS LNA - Solid-State ...

模拟CMOS集成电路第二版拉扎维 by 拉扎维 (z-lib.org)

模拟CMOS集成电路第二版拉扎维 by 拉扎维 (z-lib.org)

Scaling <formula formulatype="inline"><tex Notation="TeX">$LC$</tex></formula> Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance

Scaling <formula formulatype="inli[..] Notation="TeX">$L[..] ...

Shih-An Yu & Peter R. Kinget

Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level

Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture ...

适合通信应用的低功耗55纳米12 省略 0 MSps双通道流水线型ADC 陈宏铭

适合通信应用的低功耗55纳米12 省略 0 MSps双通道流水线型ADC 陈宏铭

Handbook of Power Management Circuits-Haruo Kobayashi

Handbook of Power Management Circuits-Haruo Kobayashi

Category: Power over Data Lines

IEEE Standard for Ethernet

IEEE Standard for Ethernet