393747_Print.indd
0009172
Constraining Designs for Synthesis and Timing Analysis A Practical ...
未知
LDO模拟集成电路设计
集成电路原理与设计 教材
ADC-based Receivers for Wireline Communication
通信原理 第7版
樊昌信，曹丽娜编著
IEEE Standard for Information Technology—Teleco[..] and information ...
LAN/MAN Standards Committee of the IEEE Computer Society
半导体器件物理与工艺（第三版）参考答案
USER
教材：李庆扬数值分析-第五版
Sahrling M. Analog Circuit Simulators for Integrated Circuit ...
Session 25
TWO-STAGE FULLY-DIFFERENTIAL OPAMPS
Vishal Home PC
Session 13: Cyro-CMOS for Quantum Computing
A low-power small-area /spl plusmn/7.28-ps-ji[..] 1-GHz DLL-based ...
Chulwoo Kim & In-Chul Hwang & Sung-Mo Kang
A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with ...
IEEE
DDR3存储器接口电路的设计与实现[..]
asicon.2009.53514[..] Power Supply Rejection
CN104391533A-High[..] (power supply rejection ratio) LDO (low ...
ADS2008射频电路设计与仿真实例
徐兴福 著