高数第七版 下册
未知
7 Series FPGAs Gen2 Integrated Block for PCIe to AXI4-Lite Bridge ...
Xilinx, Inc.
PrimeWave� Design Environment User Guide
Inc. Synopsys
2014 PhD-Thesis BAG A Designer-Oriented Framework for the Development ...
ISSCC2021-SC3-Clo[..] Clock Distribution, and Clock Management ...
CMOS射频集成电路分析与设计 (池保勇, 余志平, 石秉学) (z-lib.org)
CN106357266B-华为20[..]
Fundamentals of Layout Design for Electronic Circuits
Jens Lienig Juergen Scheible
Microsoft Word - CummingsSNUG2008B[..]
cliffc
Numerical Methods for Ordinary Differential Equations by J. ...
Computational electromagnetism variational formulations, complementarity, ...
数值计算方法 (2)
Session 26V
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai
Dracula Reference
Inc. Cadence Design Sys tems
Single miller capacitor frequency compensation technique for ...
基于功耗优化的Pipelined+[..] (1)
LDO设计小结二
zeng zhen
StarRC User Guide and Command Reference
Synopsys, Inc.