Digital Logic and Computer Design
M. MORRIS MANO
CMOS模拟集成电路版图设计与验证 基于Cadence Virtuoso与Mentor Calibre
尹飞飞
低压低功耗CMOS带隙电压基准及启[..] 许长喜
未知
Diva Reference
Inc. Cadence Design Sys tems
一种应用于LDO的高性能过温保护电路设计
ISSCC2021-T11-Ult[..] Power Wireless Receiver Design
RC OSCILLATOR WITH ADDITIONAL NVERTER IN SERIES WITH CAPACTOR
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai
数值分析 第五版 (李庆扬 王能超 易大义) (z-lib.org)
openofdm-readthed[..]
Advanced_Signal_I[..]
基于一种SIFT优化算法的图像检索
雨林木风
Cadence高速电路板设计与仿真 信号与电源完整性分析 第5版
A gm/ID Based Methodology for the Design of CMOS Analog Circuits ...
IEEE
Spectre FX Circuit Simu lator User Guide
模拟CMOS集成电路设计 第2版14609998
Simulating Switched-Capacitor Filters with SpectreRF
Ken Kundert
Embedded Mixed-Signal IP Development Methodology in 90nm CMOS ...
Rakesh H. Patel & William Bereza