Session 1: Plenary Session — Invited Papers
未知
A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Yin-Zu Lin
CN103036558B-SMIC[..]
The Problem of PLL Power Consumption
Behzad Razavi
EE214B Advanced Analog Integrated Circuit Design Winter2016 ...
CMOS: Circuit Design, Layout, and Simulation
R. Jacob Baker
一种动态零点补偿的LDO线性稳压器设计
2010_FrontMatter_[..]
Steve Bonney
HarmonicBalance
Front Matter
SHANTHI PAVAN, RICHARD SCHREIER & GABOR C. TEMES
CMOS单片LDO线性稳压器的设计
半导体器件物理与工艺（第三版）参考答案
USER
相位噪声jitter基本定义
yzx
jssc.2005.Replica Compensated Linear Regulators for PLLs
Electromagnetic Waves
Carlo G. Someda
Session 32: Frequency Synthesizers
RF Microelectronics 2nd
393747_Print.indd
0009172
Frequency Reconfigurable mm-Wave Power Amplifier With Active ...
Chandrakanth R. Chappidi & Kaushik Sengupta