A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with ...
IEEE
ESD Design and Synthesis (1)
未知
Session 30
Physical design essentials an ASIC design implementation perspective ...
模拟集成电路的分析与设计格雷 第四版
锁相环(PLL)电路设计与应用
(日)远坂俊昭 著 何希才译
共源共栅实验五
USER
Nano-scale CMOS Analog Circuits: Models and CAD Techniques for ...
Pandit, Soumya
DUTY CYCLE CORRECTION CIRCUITRY
低噪声快速建立的全片内LDO设计
Oscillator phase noise: a tutorial
T.H. Lee;A. Hajimiri
PLL Perfomance, Simulation, and Design
Dean Banerjee
COMS集成锁相环电路设计
计算电磁学 by 王秉中,邵维 (z-lib.org)
CNKI
e采样与adc
A 2-dB noise figure 900-MHz differential CMOS LNA - Solid-State ...
USB 2.0
hevryjiang
High Efficiency RF and Microwave Solid State Power Amplifiers
Paolo Colantonio, Franco Giannini & Ernesto Limiti
Low-Cost Low-Power 2.4 GHz RF Transceiver datasheet (Rev. C)
Texas Instruments, Incorporated [SWRS040,C