开关电容电路 从入门到精通
未知
Dracula Reference
Inc. Cadence Design Sys tems
LDO设计论文
Zhangwen Tang
Session 27
Sampled Systems and the Effects of Clock Phase Noise and Jitter ...
Analog Devices, Inc.
自动控制原理与设计（第6版） (富兰克林、鲍威尔。李中华 译) (Z-Library)
微波工程
David M. Pozar
Session 11: Advanced Wireline Links and Techniques
2005 Book ClockGeneratorsFo[..]
拉扎维《CMOS集成电路设计》答案手写版
《Linux从初学到精通》.(张勤[..]
Verilog数字VLSI设计教程
【作 者】李林编著
EE214: Analog Integrated Circuit Design
murmann
CMOS射频集成电路分析与设计 (池保勇, 余志平, 石秉学) (z-lib.org)
Session 33: High-Voltage, GaN and Wireless Power
运算放大器 理论与设计 9影印版 （荷）惠意欣著
Enhanced phase noise modeling of fractional-N frequency synthesizers
H. Arora;N. Klemmer;J.C. Morizio;P.D. Wolf
ch3_pnjunction
Claudio Talarico
Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller ...
Shih-An Yu & Peter R. Kinget
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop ...
Yongsun Lee & Taeho Seong & Seyeon Yoo & Jaehyouk Choi
A 76 dB 1.7 GHz 0.18 m CMOS Tunable TIA Using Broadband Current ...
Hossein Miri Lavasani & Wanling Pan & Brandon Harrington & Reza Abdolvand & Farrokh Ayazi
Scaling <formula formulatype="inli[..] Notation="TeX">$L[..] ...
Noise and Spur Comparison of Delta-Sigma Modulators in Fractional-N ...
Bo Zhou & Yao Li & Fuyuan Zhao