VLSI Physical Design: From Graph Partitioning to Timing Closure
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Smoothing the Way for Digital Phase-Locked Loops: Clock Generation ...
Cheng-Ru Ho & Mike Shuo-Wei Chen
一种低温漂CMOS带隙基准电压源的设计 陈碧
未知
tcsii.2005.A new modeling and optimization of gain-boosted cascode ...
LDO降压转换器的稳定性分析
高效率电源管理集成电路设计技术研究
Digital Logic and Computer Design
M. MORRIS MANO
带隙基准电路的研究
<CCC6B3A4CEC4>
ESD Design and Synthesis (1)
A low-power small-area /spl plusmn/7.28-ps-ji[..] 1-GHz DLL-based ...
Chulwoo Kim & In-Chul Hwang & Sung-Mo Kang
asicon.2009.53514[..] Power Supply Rejection
Gabriel Alfonso Rincon-Mora
Voltage References From Diodes to Precision High-Order Bandgap ...
NONE
TOM
模拟集成电路的分析与设计 格雷 839页 76M 高清书签版
PCI Express Base r3.0
CN106656160A-上海集成[..]
方法论篇--修改稿(更新).PDF
zhangliqian
Matching Analysis and the Design of Low Offset Amplifiers