一种基于斩波调制的低压高精度CMO[..] 刘帘曦
未知
Session 3: Highlighted Chip Releases: Modern Digital SoCs
共源共栅实验五
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CMOS模拟集成电路设计与仿真实例[..] ADE
Razavi Analog CMOS
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Wenzha Yang & Yi Zhang & Enwen Dai & ZhiLin Feng & Wei Li
低压低功耗CMOS带隙电压基准及启[..] 许长喜
一种极低静态电流LDO线性稳压器的设计
Algorithms for VLSI Physical Design Automation, 3E
Naveed Sherwani
2002 Book On-ChipESDProtect[..]
Session 3
ADS基础与低噪放设计
kj3
深亚微米FPGA结构与CAD设计 12083165 2
Spice-Oriented Nonlinear Circuit Analysis Using Harmonic Balance ...
NCSP'09
COMS集成锁相环电路设计
HIGH QUALITY PARALLEL RESONANCE OSCILLATOR
相位噪声、通行链路预算
yzx
ISSCC2021-SC1-Int[..] to PLLs Phase Noise, Modeling, and Key ...
Enhanced phase noise modeling of fractional-N frequency synthesizers
H. Arora;N. Klemmer;J.C. Morizio;P.D. Wolf