理工书库 lilin | Category: IEEE Journal of Solid-State Circuits;2002;37;11;10.1109/JSSC.2002.803936

Discover (Random Books)

SAR ADC-MIT

SAR ADC-MIT

Digital Control of Dyanmic Systems 3rd ed - G. Franklin, J. Powell, M. Workman (A-W, 1998) WW.djvu

Digital Control of Dyanmic Systems 3rd ed - G. Franklin, J. ...

Sigma-Delta ADCs - Tutorial | Maxim Integrated

Sigma-Delta ADCs - Tutorial | Maxim Integrated

Session 12

Session 12

APR8 - Principles of Sigma-Delta Modulation for Analog-to-Digital Converters

APR8 - Principles of Sigma-Delta Modulation for Analog-to-Digital ...

PrimeSim� EMIR Reference Manual

PrimeSim� EMIR Reference Manual

Pieter Harpe, Andrea Baschirotto, Kofi A. A. Makinwa eds. High-Performance AD and

Pieter Harpe, Andrea Baschirotto, Kofi A. A. Makinwa eds. High-Performance ...

ISSCC2021-SC1-Introduction to PLLs Phase Noise, Modeling, and Key Wireless Design Considerations

ISSCC2021-SC1-Int[..] to PLLs Phase Noise, Modeling, and Key ...

DCDC变换器工作原理及设计

DCDC变换器工作原理及设计

tcsii.2005.A new modeling and optimization of gain-boosted cascode amplifier for high-speed and low-voltage applications

tcsii.2005.A new modeling and optimization of gain-boosted cascode ...

WLAN射频接收机集成电路设计与研究

WLAN射频接收机集成电路设计与研究

Microsoft PowerPoint - Loop Stability Analysis_V2

Microsoft PowerPoint - Loop Stability Analysis_V2

现代控制系统第八版

现代控制系统第八版

一种高摆率低功耗无片外电容的LDO设计

一种高摆率低功耗无片外电容的LDO设计

Understanding Delta-Sigma Data Converters 2nd edition

Understanding Delta-Sigma Data Converters 2nd edition

SHANTHI PAVAN, RICHARD SCHREIER & GABOR C. TEMES

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai

Simulating Switched-Capacitor Filters with SpectreRF

Simulating Switched-Capacitor Filters with SpectreRF

一种极低静态电流LDO线性稳压器的设计

一种极低静态电流LDO线性稳压器的设计

Category: IEEE Journal of Solid-State Circuits;2002;37;11;10.1109/JSSC.2002.803936

A low-power small-area /spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

A low-power small-area /spl plusmn/7.28-ps-ji[..] 1-GHz DLL-based ...

Chulwoo Kim & In-Chul Hwang & Sung-Mo Kang