Scaling <formula formulatype="inli[..] Notation="TeX">$L[..] ...
Shih-An Yu & Peter R. Kinget
Session 15: Compute-in-Memory Processors for Deep Neural Networks
未知
数值分析
CMOS模拟集成电路设计与仿真实例[..]
Design Procedure for Two-Stage CMOS Transconductance Operational ...
NumericalAnalysis[..]
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
Session 36: Hardware Security
802.11 无线权威指南
LAN/MAN Standards Committee of the IEEE Computer Society
SARADC设计
李福乐
无电容型LDO的研究现状与进展
教材：李庆扬数值分析-第五版
Computational Methods for Electromagnetic Phenomena
Cai, Wei
Session 13
Microsoft Word - 0TitlePageVbook.doc
VC
Keliu Shu-2005 CMOS PLL Synthesizers Analysis and Design
射频集成电路
John
CN201887731U-可修调的[..] 振荡电路
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...
D.J. Foley;M.P. Flynn