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Fundamentals of Digital Logic with Verilog Design, THIRD EDITION

Fundamentals of Digital Logic with Verilog Design, THIRD EDITION

Stephen Brown & Zvonko Vranesic

共源共栅实验五

共源共栅实验五

THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN PHY

THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN ...

hfss3dlayout

hfss3dlayout

数值分析基础（第三版） (关治、陆金甫) (z-lib.org)

数值分析基础（第三版） (关治、陆金甫) (z-lib.org)

Session 33: High-Voltage, GaN and Wireless Power

Session 33: High-Voltage, GaN and Wireless Power

微波工程（第四版） (David M.Pozar) (Z-Library)

微波工程（第四版） (David M.Pozar) (Z-Library)

Sigma-Delta Converters. Practical Design Guide (José M. de la Rosa) (Z-Library)

Sigma-Delta Converters. Practical Design Guide (José M. de la ...

393747_Print.indd

393747_Print.indd

硅基压控振荡器的研究与设计电子科技大学彭羽

硅基压控振荡器的研究与设计电子科技大学彭羽

CMOS Fractional-N Synthesizers: Design for High Spectral Purity and Monolithic Integration (The Springer International Series in Engineering and Computer Science)

CMOS Fractional-N Synthesizers: Design for High Spectral Purity ...

Bram De Muer & Michiel Steyaert

数值分析（第5版）习题解答 (李庆扬) (z-lib.org)

数值分析（第5版）习题解答 (李庆扬) (z-lib.org)

Cadence高速电路板设计

Cadence高速电路板设计

深入理解LINUX虚拟内存管理

深入理解LINUX虚拟内存管理

（爱尔兰）MEL GORMAN著

VLSI Physical Design: From Graph Partitioning to Timing Closure

VLSI Physical Design: From Graph Partitioning to Timing Closure

Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu

Virtuoso Visualization and Analysis XL User Guide

Virtuoso Visualization and Analysis XL User Guide

Inc. Cadence Design Sys tems

参考书芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立

参考书芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立

Phillip E. Allen-CMOS Analog Circuit Design

Phillip E. Allen-CMOS Analog Circuit Design

Category: Computer-aided circuit analysis

Relationship between frequency response and settling time of operational amplifiers

Relationship between frequency response and settling time of ...

B.Y.T. Kamath, R.G. Meyer & P.R. Gray