Keliu Shu-2005 CMOS PLL Synthesizers Analysis and Design
未知
Design of class AB output stages using the structural methodology
V. Ivanov & I. Filanovsky
LOCK DETECTION CIRCUIT AND LOCK (56) Oct. 18, 2011 References ...
Allen CMOS模拟集成电路设计解答
Analog-to-Digital Conversion 3rd
The Problem of PLL Power Consumption
Behzad Razavi
开关电源设计 第3版
(美)普利斯曼,比利斯,莫瑞著
CMOS 射频集成电路分析与设计
Computational Intelligence in Analog and Mixed-Signal (AMS) ...
AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)
Xilinx, Inc.
LINEAR SYSTEMS AND SIGNALS
B. P. Lathi & R. A. Green
Session 16
EDA与IC设计 CMOS集成电路后端设计与实战
刘峰编著
Session 32: Frequency Synthesizers
Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture ...
高精度、快速瞬态响应LDO电路设计
xCalibrate Batch User's Manual
Siemens Industry Software
Calibre® PERC User's Manual
Analog IC Design with Low-Dropout Regulators, Second Edition
Www.Yutou.Org Ebook Team!