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高效率电源管理集成电路设计技术研究

高效率电源管理集成电路设计技术研究

两种新型CMOS带隙基准电路程军

两种新型CMOS带隙基准电路程军

Flipping the CMOS Switch

Flipping the CMOS Switch

Xue Jun Li & Yue Ping Zhang

拉扎维数据转换器设计原版

拉扎维数据转换器设计原版

CMOS模拟集成电路3艾伦-英文版

CMOS模拟集成电路3艾伦-英文版

Scaling <formula formulatype="inline"><tex Notation="TeX">$LC$</tex></formula> Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance

Scaling <formula formulatype="inli[..] Notation="TeX">$L[..] ...

Shih-An Yu & Peter R. Kinget

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...

D.J. Foley;M.P. Flynn

Computational electromagnetism variational formulations, complementarity, edge elements by Alain Bossavit, Isaak D. Mayergoyz (z-lib.org)

Computational electromagnetism variational formulations, complementarity, ...

应用于流水线ADC的比较器的设计与研究

应用于流水线ADC的比较器的设计与研究

集成电路版图设计

集成电路版图设计

余华，师建英编著

NoiseDesign.dvi

NoiseDesign.dvi

JESD204 v7.2 LogiCORE IP Product Guide (PG066)

JESD204 v7.2 LogiCORE IP Product Guide (PG066)

ISSCC2017-24 Visuals(2)

ISSCC2017-24 Visuals(2)

模拟CMOS集成电路设计答案(拉扎维)

模拟CMOS集成电路设计答案(拉扎维)

Calibre® DESIGNrev Layout Viewer User's Manual

Calibre® DESIGNrev Layout Viewer User's Manual

Siemens Industry Software

Sampled Systems and the Effects of Clock Phase Noise and Jitter Application Note (AN-756)

Sampled Systems and the Effects of Clock Phase Noise and Jitter ...

Analog Devices, Inc.

Finite element analysis with error estimators an introduction to the FEM and adaptive error analysis for engineering students (J. E. Akin) (Z-Library)

Finite element analysis with error estimators an introduction ...

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