SAR ADC-MIT
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LDO与VLDO的设计原理及性能测试
一种超低静态功耗LDO的设计
Cadence SKILL Lan guage Reference
Inc. Cadence Design Sys tems
Design of Analog CMOS Integrated Circuits, Second Edition
Behzad Razavi
Nonlinear Hybrid Continuous/Discre[..] Models (Atlantis Studies ...
Marat Akhmet
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...
D.J. Foley;M.P. Flynn
AMPLIFIER ARCHITECTURE AND APPLICATION THEREOF TO A BAND-GAP ...
Accurate and Rapid Measurement of IP2 and IP3
Ken Kundert
普通高等教育“十一五”国家级规划教材 现代控制理论 （第三版）
刘豹 唐万生主编
Handbook of Power Management Circuits
计算电磁学要论 by 盛新庆 (z-lib.org)
CNKI
一种大电流LDO稳压器的设计
Session 7: Imagers and Range Sensors
【汉化】Static Timing Analysis for Nanometer DesignsA Practical ...
Smoothing the Way for Digital Phase-Locked Loops: Clock Generation ...
Cheng-Ru Ho & Mike Shuo-Wei Chen
通信原理 第7版
樊昌信，曹丽娜编著
一款轨到轨输入 输出运算放大器的设计与研究 辛国松
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