Katsuhiko Ogata
dynstab2/ThePirateBay
A 76 dB 1.7 GHz 0.18 m CMOS Tunable TIA Using Broadband Current ...
Hossein Miri Lavasani & Wanling Pan & Brandon Harrington & Reza Abdolvand & Farrokh Ayazi
相位噪声jitter基本定义
yzx
工作在亚阈值区CMOS OTA的研究
未知
Charge Pump Circuit Design [Pan, Feng and Samaddar, Tapan] Good ...
LDO低输出噪声的分析与优化设计 朱勤为
CMOS Sigma-Delta Converters Practical Design Guide
4<8=8AB@0B>@
Modern Semiconductor Devices for Integrated Circuits
Chenming Calvin Hu
Vivado Design Suite User Guide: Logic Simulation (UG900)
Xilinx, Inc.
高速低功耗逐次逼近型模数转换器的研[..]
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
信号分析与处理_MATLAB语言及应用
http://www.pris.edu.cn
Tradeoffs and Optimization in Analog CMOS Design
David M. Binkley
Session 28V
一种高性能无片外电容型LDO设计
Session 30
Session 22
Session 35: Adaptive Digital Techniques for Variation Tolerant ...
IEEE Standard for Ethernet