Cadence SKILL Lan guage Reference
Inc. Cadence Design Sys tems
The Design of CMOS Radio-Frequency Integrated Circuits, Second ...
Thomas H. Lee
Front Matter
SHANTHI PAVAN, RICHARD SCHREIER & GABOR C. TEMES
Design Optimization of Power and Area of Two-Stage CMOS Operational ...
Telugu Maddileti;Govindarajulu Salendra;Chandra Mohan Reddy ...
分类号 密级
USER
CMOS高性能运算放大器研究与设计
未知
GPS接收机内带镜像抑制的中频滤波器设计
高速数字电路设计中信号完整性分析与研究
Perl实例精解(原书第4版)
CMOS 带隙基准源研究-tangzhangwen
zwtang
多频段匹配自动优化
Yue Xu
PowerManagmentIC
khchen
数值分析.Timothy Sauer.图灵中文扫描版
集成电路版图设计 [陆学斌 主编] 2012年版
mssc.2015.Razavi-The StrongARM Latch
Verilog HDL Design Examples
Joseph Cavanagh
学校代码： 10246
tcheng
适宜于系统集成的高速高精度模数转换[..]
IEEE Std 1801™-2018, IEEE Standard for Design and Verification ...
Design Automation Standards Committee of the IEEE Computer Society