Session 18
未知
14990665645773625[..]
一种具有温度补偿的带隙基准源及其输[..] 何捷
ADS Interoperability for RFIC Design with ADS 2016.01
Keysight EEsof EDA
锁相环技术(第3版)——Phase[..] Techniques, Third Edition
Floyd M. Gardner 著 & 姚剑清 & 译
一种应用于LDO的高性能过温保护电路设计
全数字锁相环建模及分析代码-2014
学校代码： 10246
tcheng
Session 22
CMOS模拟集成电路设计布局仿真-[..]
CN104601160B-灿芯半导[..]
eetop.cn 线性代数及其应用（英文第四版－Gi[..] Strang
PLL WITH LOW SPURS
Spectre Circuit Simulator Components and Device Models Reference
Inc. Cadence Design Sys tems
Session 4: Processors
Session 1: Plenary Session — Invited Papers
综合与Design Compiler
阳晔
US6380806B1-Diffe[..] telescopic operational amplifier having ...
AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...
Xilinx, Inc.
AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)
JESD204 v7.2 LogiCORE IP Product Guide (PG066)
Xilinx PG153 LogiCORE IP AXI Quad Serial Peripheral Interface ...
Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet
Xilinx DS534, FIR Compiler v5.0, Data Sheet