Analog Behavioral Modeling with the Verilog-A Language
未知
Harmonic balance finite element method applications in nonlinear ...
Pyros Interactive Viewer User Guide
Inc. Synopsys
基于XILINX FPGA的OFDM通信系统基带设计
Design Procedure for Two-Stage CMOS Transconductance Operational ...
sido buck converter
Duyu Liu & Xinzhi Liu & Hao Chen & Shouming Zhong
CMOS Mixed-Signal Circuit Design, 2nd Ed
锁相环(PLL)电路设计与应用
(日)远坂俊昭 著 何希才译
集成电路设计中的电源管理技术
Founder Electronics Ltd
Session 4
Digital integrated circuit design using verilog and systemverilog ...
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai
Jespers-The gm ID Methodology, a sizing tool
CMOS-Voltage-Refe[..]
4<8=8AB@0B>@
一种带过温保护和折返电流限的LDO设计
An Engineer's Guide to Automated Testing of High-Speed Interfaces
Hubert Werkmann Jose Moreira
电子电路的计算机辅助分析与设计方法.汪蕙
ISSCC2021 Session 29
Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet
Xilinx, Inc.
Xilinx DS249 LogiCORE IP CORDIC v4.0, Data Sheet,
Xilinx DS534, FIR Compiler v5.0, Data Sheet