Vivado Design Suite User Guide: Logic Simulation (UG900)
Xilinx, Inc.
集成电路版图设计
余华，师建英编著
Session 7: Imagers and Range Sensors
未知
带隙基准电路的研究
<CCC6B3A4CEC4>
Session 11: Advanced Wireline Links and Techniques
ISSCC2021-SC4-Pro[..] Clock Generation, Distribution, and Clock ...
ISSCC2021-1 3
线性代数及其应用（第5版－Gilbert Strang
Switching Power Supplies A to Z
Sanjaya_Maniktala
Modeling Jitter in PLL-based Frequency Synthesizers
Ken Kundert
Microsoft Word - translator_prefac[..]
Zhiping Yu
Distributed Loss-Compensation Techniques for Energy-Efficient ...
Session 14: mm-Wave Transceivers for Communication and Radar
Microsoft Word - LNA.doc
Electromagnetics for High-speed Analog and Digital Communication ...
Ali M. Niknejad
The Definitive ANTLR 4 Reference
Terence Parr
开关电容电路 从入门到精通
Low-noise monolithic amplifier design: Bipolar versus CMOS
Xilinx DS534, FIR Compiler v5.0, Data Sheet
Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet