理工书库 lilin | Category: The Xilinx LogiCORE IP CORDIC core implements a generalized coordinate rotational digital computer (CORDIC) algorithm.

Discover (Random Books)

Microstrip Filters for RFMicrowave Applications, Second Edition by JiaSheng Hong(auth.), Kai Chang(eds.) (z-lib.org)

Microstrip Filters for RFMicrowave Applications, Second Edition ...

反馈运算放大器电路的噪声分析和设计

反馈运算放大器电路的噪声分析和设计

Numerical Methods for Ordinary Differential Equations by J. C. Butcher (z-lib.org)

Numerical Methods for Ordinary Differential Equations by J. ...

Computer Arithmetic - Algorithms and Hardware Designs

Computer Arithmetic - Algorithms and Hardware Designs

一款超低噪声快速启动的CMOS带隙基准电路设计刘鸿雁

一款超低噪声快速启动的CMOS带隙[..] 刘鸿雁

MATLAB信号处理

MATLAB信号处理

Analysis and Design of Analog Integrated Circuits, 5th Edition

Analysis and Design of Analog Integrated Circuits, 5th Edition

Understanding Jitter Requirements of PLL-Based Processors Application Note (EE-261)

Understanding Jitter Requirements of PLL-Based Processors Application ...

ANALOG DEVICES INC.

Session 34: Emerging Imaging Solutions

Session 34: Emerging Imaging Solutions

Numerical Analysis

Numerical Analysis

Richard L. Burden

高精度带隙基准电压源的实现江金光

高精度带隙基准电压源的实现江金光

华侨大学模拟IC实验8 无缓冲两级运放设计

华侨大学模拟IC实验8 无缓冲两级运放设计

Linear Circuit Transfer Functions: An Introduction to Fast Analytical Techniques

Linear Circuit Transfer Functions: An Introduction to Fast Analytical ...

Christophe P. Basso

DjVu Document

DjVu Document

THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN PHY

THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN ...

Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range

Design techniques for cascoded CMOS op amps with improved PSRR ...

D.B. Ribner & M.A. Copeland

Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques [Paper] - Solid-State Circuits, IEEE Journal of

Low-Jitter Process-Independent DLL and PLL Based on Self-Biased ...

A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications

A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...

Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao

Category: The Xilinx LogiCORE IP CORDIC core implements a generalized coordinate rotational digital computer (CORDIC) algorithm.

Xilinx DS249 LogiCORE IP CORDIC v4.0, Data Sheet,

Xilinx DS249 LogiCORE IP CORDIC v4.0, Data Sheet,