A 25Gb/s PAM4 Transmitter in 90nm CMOS SOI
Author
Session 32
未知
DELAY LOCKLOOP CIRCUIT
模拟电路设计——鲁棒性设计、Sig[..] (模拟电路设计——鲁棒性设计、Si[..] (z-lib.org)
作者
12bit pipeline ADC design
简并点优化的高性能带隙基准电路 应建华
用于射频SOC芯片的低噪声高电源抑[..]
jssc.2005.Replica Compensated Linear Regulators for PLLs
Microsoft Word - 0TitlePageVbook.doc
VC
Session 25
Enhanced phase noise modeling of fractional-N frequency synthesizers
H. Arora;N. Klemmer;J.C. Morizio;P.D. Wolf
ADS射频电路设计与仿真入门及应用实例
冯新宇著
ISSCC2021-1 3
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop ...
Yongsun Lee & Taeho Seong & Seyeon Yoo & Jaehyouk Choi
bstj.1932.Nyquist, H.-Regeneration Theory
数值分析
用于低相位噪声LC VCO的低噪声可调LDO的设计
RFIC2 Razavi
Embedded Design Handbook
Intel Corporation