Verilog HDL Design Examples
Joseph Cavanagh
A compact power-efficient 3 V CMOS rail-to-rail input/output ...
IEEE
compact trimming design of a high precision reference
未知
电路分析
一种快速瞬态响应的无片外电容LDO
Design of Low Noise Amplifiers
Steve Long
ADC-based Receivers for Wireline Communication
普林斯顿概率论读本 (史蒂文．J．米勒 (Steven J. Miller)) (Z-Library)
MIPI Alliance Specification for I3C Basic, Version 1.0
MIPI Alliance & Inc.
Session 30
Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet
Xilinx, Inc.
集成电路版图设计 [陆学斌 主编] 2012年版
MOSAmpNoise.dvi
Design of Ultra Wideband Power Transfer Networks
Binboga Siddik Yarman
ISM-PLL
A 470-nA Quiescent Current and 92.7%/94.7[..] Efficiency ...
Delta-Sigma Data Converters: Theory, Design, and Simulation
GABOR C. TEMES & Steven R. Norsworthy & Richard Schreier
Ring PLL的详细设计博士论文
PCI Express PHY v1.0 LogiCORE IP Product Guide
Vivado Design Suite User Guide: Logic Simulation (UG900)
AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...
AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)
JESD204 v7.2 LogiCORE IP Product Guide (PG066)
Xilinx PG153 LogiCORE IP AXI Quad Serial Peripheral Interface ...