理工书库 lilin | Category: This core implements a JESD204B interface supporting a line rate of up to 12.5 Gb/s on 1- 12 lanes using GTX or GTH transceivers in Zynq-7000 AP SoC devices

Discover (Random Books)

一种无片外电容LDO的瞬态增强电路设计

一种无片外电容LDO的瞬态增强电路设计

基于 DLL倍频技术的 1GHz本地振荡器设计英文李金城

基于 DLL倍频技术的 1GHz本地振荡器设计英文李金城

Numerical Methods for Wave Equations in Geophysical Fluid Dynamics (Dale R. Durran (auth.)) (Z-Library)

Numerical Methods for Wave Equations in Geophysical Fluid Dynamics ...

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop ...

Yongsun Lee & Taeho Seong & Seyeon Yoo & Jaehyouk Choi

CMOS TRANSCONDUCTANCE AMPLIFIER WITH FLOATING OPERATING POINT

CMOS TRANSCONDUCTANCE AMPLIFIER WITH FLOATING OPERATING POINT

Session 22

Session 22

ISSCC2021 Session 28

ISSCC2021 Session 28

Switching Power Supplies A to Z

Switching Power Supplies A to Z

Sanjaya_Maniktala

Quantus Substrate Tech nology Characterization Manual

Quantus Substrate Tech nology Characterization Manual

Inc. Cadence Design Sys tems

Creating Qsys Components

Creating Qsys Components

Altera Corporation

A gm/ID Based Methodology for the Design of CMOS Analog Circuits andd Its Application to the S - Solid-State Circuits, IEEE Journal of

A gm/ID Based Methodology for the Design of CMOS Analog Circuits ...

模拟集成电路设计与仿真何乐年

模拟集成电路设计与仿真何乐年

模拟CMOS集成电路第二版拉扎维 by 拉扎维 (z-lib.org)

模拟CMOS集成电路第二版拉扎维 by 拉扎维 (z-lib.org)

Diva Reference

Diva Reference

Inc. Cadence Design Sys tems

The advanced part of A treatise on the dynamics of a system of rigid bodies. Being part II of a treatise on the whole subject. With numerous examples. By Edward John Routh.

The advanced part of A treatise on the dynamics of a system ...

Routh, Edward John, 1831-1907.

esd-circuits-and-devices

esd-circuits-and-[..]

Session 15

Session 15

CMOS Sigma-Delta Converters Practical Design Guide

CMOS Sigma-Delta Converters Practical Design Guide

Category: This core implements a JESD204B interface supporting a line rate of up to 12.5 Gb/s on 1- 12 lanes using GTX or GTH transceivers in Zynq-7000 AP SoC devices

JESD204 v7.2 LogiCORE IP Product Guide (PG066)

JESD204 v7.2 LogiCORE IP Product Guide (PG066)