IEEE Standard for Ethernet
未知
Modeling Jitter in PLL-based Frequency Synthesizers
Ken Kundert
RF ANALOG IC DESIGN PROJECT
ctao
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
Spectre Circuit Simulator and Accelerated Parallel Simula tor ...
Inc. Cadence Design Sys tems
AMBA AXI Protocol Specification
ARM Limited
Session 26V
gmId方法原理
基于0.13μm SOI CMOS工艺的高性能LDO设计
A CMOS Chopper Opamp with Integrated Low-Pass Filter
Perl语言入门 第六版
NONE
TOM
ADS应用详解:射频电路设计与仿真
陈艳华,李朝晖,夏玮编著
2005 Book ClockGeneratorsFo[..]
Numerical Analysis (Second Edition)
Walter Gautschi
PoleZero.dvi
Cadence PVS Developers Guide
ESD Design and Synthesis (1)
AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...
Xilinx, Inc.