FPGA 全芯片 ESD 防护设计和优化
USER
Session 15: Compute-in-Memory Processors for Deep Neural Networks
未知
Low Drop-Out Voltage Regulators: Capacitor-less Architecture ...
Joselyn Torres & Mohamed El-Nozahi & Ahmed Amer & Seenu Gopalraju & Reza Abdullah & Kamran Entesari & Edgar Sanchez-Sinencio
Session 36: Hardware Security
jssc.2005.Replica Compensated Linear Regulators for PLLs
简并点优化的高性能带隙基准电路
Design of Low Noise Amplifiers
Steve Long
Numerical Methods for Wave Equations in Geophysical Fluid Dynamics ...
4<8=8AB@0B>@
一种高性能无片外电容型LDO设计
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...
D.J. Foley;M.P. Flynn
有限元方法（第五版）第一卷 基本原理
（英）O.C.Zienkiewicz （美）R.L.Taylor著
Session 19: Optical Systems for Emerging Applications
带ESD保护结构的IO单元库的设计
线性代数及其应用（第5版－Gilbert Strang
A detailed analysis of power-supply noise attenuation in bandgap ...
Microsoft Word - RFKitDoc_v1 3.doc
alanw
Calibre® Local Printability Enhancement User's and Reference ...
Siemens Industry Software
Session 16
Embedded Peripherals IP User Guide
Intel Corporation