理工书库 lilin | Category: as part of the Vivado Design Suite

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二级密勒补偿运算放大器

二级密勒补偿运算放大器

适合通信应用的低功耗55纳米12 省略 0 MSps双通道流水线型ADC 陈宏铭

适合通信应用的低功耗55纳米12 省略 0 MSps双通道流水线型ADC 陈宏铭

摘要

模拟集成电路

模拟集成电路

Sampled Systems and the Effects of Clock Phase Noise and Jitter Application Note (AN-756)

Sampled Systems and the Effects of Clock Phase Noise and Jitter ...

Analog Devices, Inc.

2017 Book OperationalAmplifiers

2017 Book OperationalAmplif[..]

A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process

A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process

Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Yin-Zu Lin

Power systems-on-chip practical aspects of design (Allard, Bruno) (Z-Library)

Power systems-on-chip practical aspects of design (Allard, Bruno) ...

一种自参考结构的高速高精度片上时钟抖动测量系统

一种自参考结构的高速高精度片上时钟[..]

ISSCC2021 Session 28

ISSCC2021 Session 28

A 240-nA Quiescent Current, 95.8% Efficiency AOT-Controlled Buck Converter With A<sup>2</sup>-Comparator and Sleep-Time Detector for IoT Application

A 240-nA Quiescent Current, 95.8% Efficiency AOT-Controlled ...

Wenbin Huang & Lianxi Liu & Xufeng Liao & Chengzhi Xu & Yonyuan Li

Session 21

Session 21

Instruction for Camera-Ready Paper

Instruction for Camera-Ready Paper

自动控制原理第6版

自动控制原理第6版

基于CMOS工艺的负压低压差线性稳压器设计

基于CMOS工艺的负压低压差线性稳[..]

FPGA 全芯片 ESD 防护设计和优化

FPGA 全芯片 ESD 防护设计和优化

射频集成电路

射频集成电路

A 25Gb/s PAM4 Transmitter in 90nm CMOS SOI

A 25Gb/s PAM4 Transmitter in 90nm CMOS SOI

Category: as part of the Vivado Design Suite

Vivado Design Suite User Guide: Logic Simulation (UG900)

Vivado Design Suite User Guide: Logic Simulation (UG900)