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CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...
D.J. Foley;M.P. Flynn
Jespers-The gm ID Methodology, a sizing tool
Operational Amplifiers Theory and Design (Johan Huijsing (auth.)) ...
Bipolar and MOS Analog IC Design
Alan B. Grebene
开关电容电路 从入门到精通
Analog Integrated Circuit Design
Tony Chan Carusone, David A. Johns & Kenneth W. Martin
芯片I／O缓冲及ESD电路设计
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
Internal and external op-amp compensation: a control-centric ...
零点极点
Differential Equations Theory, Technique, and Practice by George ...
(EE) Razavi, Design of Analog CMOS Integrated Circuits 2nd
全单片集成的多模CMOS正交频率综[..]
LDO设计-tangzhangwen
Zhangwen Tang
X-Parameters
DAVID E. ROOT
Using ADS to simulate Noise Figure using a large-signal transistor ...
Steve Long
FinFET Modeling for IC Simulation and Design
4<8=8AB@0B>@
Design Procedure for Two-Stage CMOS Opamp using gm/ID design ...
Bakr Hesham & El-Sayed Hasaneen & Hesham F. A. Hamed