理工书库 lilin | Category: IEEE Custom Integrated Circuits Conference 2006;2006; ; ;10.1109/CICC.2006.320979

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IEEE Std 1801™-2018, IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems

IEEE Std 1801™-2018, IEEE Standard for Design and Verification ...

Design Automation Standards Committee of the IEEE Computer Society

集成电路版图设计 [陆学斌主编] 2012年版

集成电路版图设计 [陆学斌主编] 2012年版

CN101969305B-威盛电子2012-Potential conversion circuit

CN101969305B-威盛电子[..] conversion circuit

一种带过温过流过压保护的LDO设计

一种带过温过流过压保护的LDO设计

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Session 10

开关电源控制环路设计

开关电源控制环路设计

池保勇 CMOS射频集成电路分析与设计

池保勇 CMOS射频集成电路分析与设计

A precise on-chip voltage generator for a gigascale dram with a negative word-line scheme - Solid-State Circuits, IEEE Journal of

A precise on-chip voltage generator for a gigascale dram with ...

Numerical Simulation of Optical Wave Propagation With Examples in Matlab

Numerical Simulation of Optical Wave Propagation With Examples ...

Jason D. Schmidt

全差分运算放大器设计

全差分运算放大器设计

Scaling <formula formulatype="inline"><tex Notation="TeX">$LC$</tex></formula> Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance

Scaling <formula formulatype="inli[..] Notation="TeX">$L[..] ...

Shih-An Yu & Peter R. Kinget

Voltus IC Power Integrity Solution User Guide

Voltus IC Power Integrity Solution User Guide

Inc. Cadence Design Sys tems

Nonlinear Circuit Simulation and Modeling Fundamentals for Microwave Design (The Cambridge RF and Microwave Engineering Series) by José Carlos Pedro, David E. Root, Jianjun Xu, Luís Cótimos Nunes (z-lib.o

Nonlinear Circuit Simulation and Modeling Fundamentals for Microwave ...

Oversampling Delta-Sigma Data Converters lowRes Candy

Oversampling Delta-Sigma Data Converters lowRes Candy

Cadence SKILL Lan guage Reference

Cadence SKILL Lan guage Reference

Inc. Cadence Design Sys tems

一种加入动态补偿电路的快速响应LDO设计

一种加入动态补偿电路的快速响应LDO设计

ISSCC2021-1 3

ISSCC2021-1 3

基于延迟锁相环的时钟发生器设计

基于延迟锁相环的时钟发生器设计

Category: IEEE Custom Integrated Circuits Conference 2006;2006; ; ;10.1109/CICC.2006.320979

Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs

Embedded Mixed-Signal IP Development Methodology in 90nm CMOS ...

Rakesh H. Patel & William Bereza