理工书库 lilin | Category: that features three low phase-noise VCOs with a fundamental frequency range of 3.0 GHz to 6.0 GHz and a programmable dual RF output divider stage which allows coverage from 46.875 MHz to 6 GHz.

Discover (Random Books)

Session 1: Plenary Session — Invited Papers

Session 1: Plenary Session — Invited Papers

SPI Block Guide V4

SPI Block Guide V4

Freescale Semiconductor, Inc.

CN106656160A-上海集成电路研发中心2017-优化占空比的高速电平转换电路

CN106656160A-上海集成[..]

fluids-04-00159-v2

fluids-04-00159-v2

A Low Power Two Stages CMOS OpAmp

A Low Power Two Stages CMOS OpAmp

参考书芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立

参考书芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立

CN104391533A-High-PSRR (power supply rejection ratio) LDO (low dropout regulator) circuit

CN104391533A-High[..] (power supply rejection ratio) LDO (low ...

基于一种SIFT优化算法的图像检索

基于一种SIFT优化算法的图像检索

Design Optimization of Power and Area of Two-Stage CMOS Operational Amplifier Utilizing Chaos Grey Wolf Technique

Design Optimization of Power and Area of Two-Stage CMOS Operational ...

Telugu Maddileti;Govindarajulu Salendra;Chandra Mohan Reddy ...

一种具有高电源抑制比的低功耗CMOS带隙基准电压源汪宁

一种具有高电源抑制比的低功耗CMO[..] 汪宁

一种低温漂CMOS带隙基准电压源的设计陈碧

一种低温漂CMOS带隙基准电压源的设计陈碧

2005 Book ClockGeneratorsForSOCProcessor

2005 Book ClockGeneratorsFo[..]

零点极点

零点极点

A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell lib - Solid-State Circuits, IEEE Journal of

A compact power-efficient 3 V CMOS rail-to-rail input/output ...

Continuous-Time Sigma-Delta AD Conversion Fundamentals, Performance Limits and Robust Implementations by Friedel Gerfers, Maurits Ortmanns (z-lib.org)

Continuous-Time Sigma-Delta AD Conversion Fundamentals, Performance ...

ISSCC2021-SC2-PLL Architectures, Tradeoffs, and Key Application Considerations

ISSCC2021-SC2-PLL Architectures, Tradeoffs, and Key Application ...

Session 10

Session 10

一种带过温保护和折返电流限的LDO设计

一种带过温保护和折返电流限的LDO设计

Category: that features three low phase-noise VCOs with a fundamental frequency range of 3.0 GHz to 6.0 GHz and a programmable dual RF output divider stage which allows coverage from 46.875 MHz to 6 GHz.

$Wideband RF PLL fractional/integer frequency synthesizer with integrated VCOs and LDOs$

Wideband RF PLL fractional/integer frequency synthesizer with ...

STMICROELECTRONICS