理工书库 lilin | Category: phase-locked loop (PLL)

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Numerical Analysis (Richard L. Burden, J. Douglas Faires etc.) (z-lib.org) (1)

Numerical Analysis (Richard L. Burden, J. Douglas Faires etc.) ...

All-Digital Frequency Synthesizer for RF Wireless Application

All-Digital Frequency Synthesizer for RF Wireless Application

一种适用于微传感器读出电路的低噪声、低失调斩波放大器 (1)

一种适用于微传感器读出电路的低噪声[..] (1)

Fast analytical techniques for electrical and electronic circuits

Fast analytical techniques for electrical and electronic circuits

Vatche Vorperian

PowerManagmentIC

PowerManagmentIC

模拟电路版图的艺术

模拟电路版图的艺术

CMOS模拟集成电路设计与仿真实例：基于Hspice

CMOS模拟集成电路设计与仿真实例[..]

GPS接收机内带镜像抑制的中频滤波器设计

GPS接收机内带镜像抑制的中频滤波器设计

StarRC User Guide and Command Reference

StarRC User Guide and Command Reference

CMOS集成电路中静电防护电路的设计与研究

CMOS集成电路中静电防护电路的设[..]

ISSCC2021-T6-Basics of DAC-based Wireline Transmitters

ISSCC2021-T6-Basics of DAC-based Wireline Transmitters

PLL Perfomance, Simulation, and Design

PLL Perfomance, Simulation, and Design

EDA与IC设计 CMOS集成电路后端设计与实战

EDA与IC设计 CMOS集成电路后端设计与实战

CMOS带隙基准源研究现状幸新鹏

CMOS带隙基准源研究现状幸新鹏

信号与系统下第三版

信号与系统下第三版

Computing the continuous discretely. Integer-point enumeration in polyhedra Beck, Matthias Robins, Sinai (z-lib.org)

Computing the continuous discretely. Integer-point enumeration ...

S_Para_E.PM6

S_Para_E.PM6

Design Procedure for Two-Stage CMOS Opamp using gm/ID design Methodology in 16 nm FinFET Technology

Design Procedure for Two-Stage CMOS Opamp using gm/ID design ...

Bakr Hesham & El-Sayed Hasaneen & Hesham F. A. Hamed

Category: phase-locked loop (PLL)

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop ...

Yongsun Lee & Taeho Seong & Seyeon Yoo & Jaehyouk Choi