Verilog HDL Design Examples
Joseph Cavanagh
Session 17
未知
PoleZero.dvi
Pyros Interactive Viewer User Guide
Inc. Synopsys
基于ac620的fpga系统设计与[..]
Administrator
Abidi-Pan, Hui.University of California, Los Angeles
Design Optimization of Power and Area of Two-Stage CMOS Operational ...
Telugu Maddileti;Govindarajulu Salendra;Chandra Mohan Reddy ...
Session 25: DRAM
Modern Semiconductor Devices for Integrated Circuits
Chenming Calvin Hu
Analysis and Design of Transimpedance Amplifiers for Optical ...
4<8=8AB@0B>@
Internal and external op-amp compensation: a control-centric ...
COMS集成锁相环电路设计 张刚
综合与Design Compiler
阳晔
一种用于LDO的低功耗带隙基准电压源
Session 22
The Problem of PLL Power Consumption
Behzad Razavi
DDR3存储器接口电路的设计与实现[..]
CMOS射频集成电路分析与设计 (池保勇, 余志平, 石秉学)
Analysis and Design of ESD Protection for Robust Low-Power Pierce ...
Kim B. Ostman & Erlend Strandvik & Phil Corbishley & Tor Oyvind Vedal & Mika Salmi