asicon.2009.53514[..] Power Supply Rejection
未知
Universal Serial Bus 3.0 Specification
A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with ...
IEEE
拉扎维 数据转换器设计 原版 (1)
Relationship between frequency response and settling time of ...
B.Y.T. Kamath, R.G. Meyer & P.R. Gray
Session 12: Innovations in Low-Power and Secure IoT
THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN ...
iccad095
Convex Optimization in Signal Processing and Communications
Daniel P. Palomar, Yonina C. Eldar
js.2010.PFD biased with shunt regulator
硕士论文-宽带匹配网络的实频法研究
微带电路——清华
MATLAB for Control System Engineers
Rao V Dukkipati
2004Beek
a
verilog HDL那些事
akuei2
Principles of Verilog Digital Design
Wen-Long Chin
普林斯顿微积分读本(修订版)
Adrian Banner
DesignWare Synthesizable Components for AMBA 3 AXI, and AMBA ...
Synopsys, Inc.