A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
Analysis and Design of CMOS Clocking Circuits for Low Phase ...
Woorham Bae & Deog-Kyoon Jeong
高性能流水线模数转换器及其数字校准[..] 贾华宇
未知
Handbook of Algorithms for Physical Design Automation
Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar
Chap1_20160228_4.dvi
ISSCC2021 Session 29
数值分析(第5版)习题解答 (李庆扬) (z-lib.org)
Optimum Feedback Amplifier Design For Control Systems
Timothy E. Biesecker
高速数字电路设计中信号完整性分析与研究
ISSC2021 SESSION 2
Analog-Circuit-co[..]
UVM实战(卷Ⅰ)
张强编著
A 240-nA Quiescent Current, 95.8% Efficiency AOT-Controlled ...
Wenbin Huang & Lianxi Liu & Xufeng Liao & Chengzhi Xu & Yonyuan Li
半导体物理学 (第七版)
Session 5: Analog Interfaces
宽带可变增益放大器的研究与设计
Understanding Phase Noise in LC VCOs
A Key Problem in RF Integrated Circuits
ISSCC2021-T11-Ult[..] Power Wireless Receiver Design
IEEE Std 802.11g-2003 [Amendment to IEEE Std 802.11, 1999 Edition ...
LAN/MAN Standards Committee of the IEEE Computer Society