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一种基于斩波调制的低压高精度CMOS带隙基准源刘帘曦

一种基于斩波调制的低压高精度CMO[..] 刘帘曦

运放chopper基本原理

运放chopper基本原理

A precise on-chip voltage generator for a gigascale dram with a negative word-line scheme - Solid-State Circuits, IEEE Journal of

A precise on-chip voltage generator for a gigascale dram with ...

COMS集成锁相环电路设计

COMS集成锁相环电路设计

Microwave Circuit Design: A Practical Approach Using ADS

Microwave Circuit Design: A Practical Approach Using ADS

Yeom, Kyung-Whan

天线理论与设计第2版

天线理论与设计第2版

W.L) 斯塔兹曼(Stutzman (作者) & 蒂尔 (Thiele.G.A) (作者) & 朱守正 (译者)

频率补偿研究心得

频率补偿研究心得

Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip Communication

Distributed Loss-Compensation Techniques for Energy-Efficient ...

基于 DLL倍频技术的 1GHz本地振荡器设计英文李金城

基于 DLL倍频技术的 1GHz本地振荡器设计英文李金城

High-Speed Architecture for a Programmable Frequency Divider and a Dual-Modulus Prescaler - Solid-State Circuits, IEEE Journal of

High-Speed Architecture for a Programmable Frequency Divider ...

Spectre RelXpert Reli ability Simulator User Guide

Spectre RelXpert Reli ability Simulator User Guide

Inc. Cadence Design Sys tems

Session 25

Session 25

FinFET Devices for VLSI Circuits and Systems

FinFET Devices for VLSI Circuits and Systems

数字滤波器的MATLAB与FPGA实现（第2版）

数字滤波器的MATLAB与FPGA[..]

IEEE Std 802.11ac™-2013, IEEE Standard for Information technology—Telecommunications and information exchange between systems—Local and metropolitan area networks—Specific requirements—Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications—Amendment 4: Enhancements for Very High Throughput for Operation in Bands below 6 GHz

IEEE Std 802.11ac™-2013, IEEE Standard for Information technology—Teleco[..] ...

LAN/MAN Standards Committee of the IEEE Computer Society

$Wideband RF PLL fractional/integer frequency synthesizer with integrated VCOs and LDOs$

Wideband RF PLL fractional/integer frequency synthesizer with ...

STMICROELECTRONICS

Constraining Designs for Synthesis and Timing Analysis A Practical Guide to Synopsys Design Constraints (SDC) (Sridhar Gangadharan, Sanjay Churiwala (auth.)) (z-lib.org)

Constraining Designs for Synthesis and Timing Analysis A Practical ...

一个全差分运放电路的设计

一个全差分运放电路的设计

Category: Coregen

Xilinx DS534, FIR Compiler v5.0, Data Sheet

Xilinx DS534, FIR Compiler v5.0, Data Sheet

Xilinx DS249 LogiCORE IP CORDIC v4.0, Data Sheet,

Xilinx DS249 LogiCORE IP CORDIC v4.0, Data Sheet,