Session 8: Ultra-High-Speed Wireline
未知
控制之美 卷1 (王天威) (Z-Library)
LOCK DETECTION CIRCUIT AND LOCK (56) Oct. 18, 2011 References ...
Power supply rejection ratio in operational transconductance ...
IEEE
COMS集成锁相环电路设计
一种超低静态功耗LDO的设计
模拟电路设计——鲁棒性设计、Sig[..] (模拟电路设计——鲁棒性设计、Si[..] (z-lib.org)
作者
高精度sigma-delta ADC设计研究与实现
离散数学及其应用
The Art of Analog Layout, Second Edition
Alan Hastings
Numerical Analysis
Richard L. Burden
DjVu Document
Gustavo
The Method of Moments in Electromagnetics
Walton C. Gibson
ISSCC2021 Session 17
数字通信同步技术的MATLAB与F[..] Altera Verilog版 [杜勇 编著] 2015年版
Distributed MOS varactor biasing for VCO gain equalization in ...
J. Mira & T. Divel & S. Ramet & J.-B. Begueret & Y. Deval
CMOS模拟集成电路设计与仿真实例[..] ADE
24位96KSPSΣ-Δ调制器的设计
CBJ
Xilinx PG153 LogiCORE IP AXI Quad Serial Peripheral Interface ...
Xilinx, Inc.
Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet
Xilinx DS534, FIR Compiler v5.0, Data Sheet
JESD204 v7.2 LogiCORE IP Product Guide (PG066)