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Phase-Locked Loops Design, Simulation, and Applications (Roland E. Best) (Z-Library)

Phase-Locked Loops Design, Simulation, and Applications (Roland ...

一种应用于MCU待机模式的超低功耗LDO设计

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Wishbone B4

Wishbone B4

Jespers-The gm ID Methodology, a sizing tool

Jespers-The gm ID Methodology, a sizing tool

深入Linux内核架构

深入Linux内核架构

Middlebrook Part 1

Middlebrook Part 1

Numerical Algorithms: Methods for Computer Vision, Machine Learning, and Graphics

Numerical Algorithms: Methods for Computer Vision, Machine Learning, ...

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Microsoft Word - translator_prefac[..]

分类号密级

分类号密级

Altera系列FPGA芯片IP核详解

Altera系列FPGA芯片IP核详解

Modelling Methodologies in Analogue Integrated Circuit Design

Modelling Methodologies in Analogue Integrated Circuit Design

Günhan Dündar & Mustafa Berke Yelten (Editors)

概率论及其应用第2卷 (威廉·费勒) (Z-Library)

概率论及其应用第2卷 (威廉·费勒) (Z-Library)

Processor Design System-on-Chip Computing for ASICs and FPGAs (Jari Nurmi) (Z-Library)

Processor Design System-on-Chip Computing for ASICs and FPGAs ...

LDO设计小结二

LDO设计小结二

SPICE Circuit Handbook (Steven M. Sandler, Charles Hymowitz) (Z-Library)

SPICE Circuit Handbook (Steven M. Sandler, Charles Hymowitz) ...

一种应用于LDO的可编程电流限电路设计

一种应用于LDO的可编程电流限电路设计

Analog Integrated Circuit Design Automation Placement, Routing and Parasitic Extraction Techniques (Horta, NunoLourenço, NunoMartins, Ricardo) (Z-Library)

Analog Integrated Circuit Design Automation Placement, Routing ...

DjVu Document

DjVu Document

Category: This core implements a JESD204B interface supporting a line rate of up to 12.5 Gb/s on 1- 12 lanes using GTX or GTH transceivers in Zynq-7000 AP SoC devices

JESD204 v7.2 LogiCORE IP Product Guide (PG066)

JESD204 v7.2 LogiCORE IP Product Guide (PG066)