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SystemVerilog验证测试平台编写指南

SystemVerilog验证测试平台编写指南

IEEE Standard for Information Technology—Telecommunications and information exchange between systems—LANs and MANs—Specific requirements—Part 11: WLAN MAC and PHY Specifications—Amendment 5: Enhancements for Higher Throughput

IEEE Standard for Information Technology—Teleco[..] and information ...

LAN/MAN Standards Committee of the IEEE Computer Society

集成电路版图设计 [陆学斌主编] 2012年版

集成电路版图设计 [陆学斌主编] 2012年版

一种极低静态电流LDO线性稳压器的设计

一种极低静态电流LDO线性稳压器的设计

一种基于LDO稳压器的带隙基准电压源设计

一种基于LDO稳压器的带隙基准电压源设计

ISSCC2021-SC3

ISSCC2021-SC3

Fundamentals of Digital Logic with Verilog Design, THIRD EDITION

Fundamentals of Digital Logic with Verilog Design, THIRD EDITION

Stephen Brown & Zvonko Vranesic

Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level

Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture ...

CMOS带隙基准源研究现状幸新鹏

CMOS带隙基准源研究现状幸新鹏

一种具有温度补偿高电源抑制比的带隙基准源何捷 (1)

一种具有温度补偿高电源抑制比的带隙基准源何捷 (1)

Session 23

Session 23

MOSAmpNoise.dvi

MOSAmpNoise.dvi

Design Procedure for Two-Stage CMOS Opamp using gm/ID design Methodology in 16 nm FinFET Technology

Design Procedure for Two-Stage CMOS Opamp using gm/ID design ...

Bakr Hesham & El-Sayed Hasaneen & Hesham F. A. Hamed

FREQUENCY DIVIDINGAPPARATUS AND RELATED METHOD

FREQUENCY DIVIDINGAPPARATUS AND RELATED METHOD

IEEE Std 802.11ac™-2013, IEEE Standard for Information technology—Telecommunications and information exchange between systems—Local and metropolitan area networks—Specific requirements—Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications—Amendment 4: Enhancements for Very High Throughput for Operation in Bands below 6 GHz

IEEE Std 802.11ac™-2013, IEEE Standard for Information technology—Teleco[..] ...

LAN/MAN Standards Committee of the IEEE Computer Society

一种适用于高压电源管理的无输出电容自基准低压差线性稳压器

一种适用于高压电源管理的无输出电容[..]

AN827_RevA.fm

AN827_RevA.fm

一种自参考结构的高速高精度片上时钟抖动测量系统

一种自参考结构的高速高精度片上时钟[..]

Category: This core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.

AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)

AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)