Verilog数字系统设计教程
未知
高性能小数分频频率合成技术 刘祖深 压缩版
Abraham uta GPIO ESD
Administrator
PrimeSim� HSPICE® User Guide: Signal Integrity Modeling and ...
Inc. Synopsys
带隙基准电路的研究
<CCC6B3A4CEC4>
基准源、噪声、开关电容及Monte Carlo仿真
Design considerations of recent advanced low-voltage low-temperature-c[..] ...
集成电路设计中的电源管理技术
Founder Electronics Ltd
EE145C UCSB RFCMOS Communication Circuits and Systems g
DCDC变换器工作原理及设计
MPS
低压差电压调节器技术发展动态
Digital Design Netlisting and Simulation SKILL Refer ence
Inc. Cadence Design Sys tems
Understanding Jitter Requirements of PLL-Based Processors Application ...
ANALOG DEVICES INC.
一个全差分运放电路的设计
Modeling Jitter in PLL-based Frequency Synthesizers
Ken Kundert
Microsoft PowerPoint - PLLnoise_jitter02[..] [相容模式]
cwhsu
ESD Design and Synthesis (1)
A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier - Solid-State Circuits, ...
IEEE
A Single-Trim CMOS Bandgap Reference With aInaccuracy of0.15% ...
Guang Ge & Cheng Zhang & Gian Hoogzaad & Kofi A. A. Makinwa