CN105763219A-2016[..]
未知
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
ISSCC2021-T1-Fund[..] of RF and Mm-Wave Power Amplifier Designs
Analog-to-Digital Conversion 3rd
Compact Heat Exchangers – Analysis, Design and Optimization ...
Analog Circuit Design Volume Three
Bob Dobkin,John Hamburger
Analog Behavioral Modeling with the Verilog-A Language
Analysis and design of monolithic, high PSR, linear regulators ...
Calibre xACT Quick Reference
Siemens Industry Software
Fundamentals of Digital Logic with Verilog Design, THIRD EDITION
Stephen Brown & Zvonko Vranesic
CMOS模拟集成电路设计与仿真实例 基于Hspice
HIGH QUALITY PARALLEL RESONANCE OSCILLATOR
Gray Hurst Analysis and Design of Analog Integra
Computational electromagnetism variational formulations, complementarity, ...
EDA与IC设计 CMOS集成电路后端设计与实战
刘峰编著
精通开关电源设计(第2版)
Katsuhiko Ogata
dynstab2/ThePirateBay
ISSCC2021-T4-Meas[..] and Evaluating the Security Level of ...
Standard Verification Rule Format (SVRF) Manual 2020
Mentor Graphics Corporation