JSSC 202212
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Distributed MOS varactor biasing for VCO gain equalization in ...
J. Mira & T. Divel & S. Ramet & J.-B. Begueret & Y. Deval
Fundamentals of Digital Logic with Verilog Design, THIRD EDITION
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Digital Design Netlisting and Simulation SKILL Refer ence
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Amplifiers, Comparators, Multipliers, Filters, and Oscillators; ...
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一种10 ppm oC低压CMOS带隙电压基准源设计 朱樟明
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LDO设计论文
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HIGH SPEED AND LOW POWER DYNAMIC LATCH COMPARATOR
二级运放设计
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Verilog数字系统设计教程
CMOS Sigma-Delta Converters Practical Design Guide
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开关电源设计 第3版
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控制之美 卷1 (王天威) (Z-Library)
FinFET Modeling for IC Simulation and Design
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A simple three-terminal IC bandgap reference
A.P. Brokaw